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| author | Likun Gao <Likun.Gao@amd.com> | 2020-05-01 22:24:33 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-23 21:33:48 +0200 |
| commit | 4005809bb1f31fd3c23b42c24c90b15ed72746c0 (patch) | |
| tree | 17c795c14186163b682823e16cb00eb4cb332e0d /drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | |
| parent | drm/amdgpu: add GC 10.3 NOALLOC registers (diff) | |
| download | linux-4005809bb1f31fd3c23b42c24c90b15ed72746c0.tar.xz linux-4005809bb1f31fd3c23b42c24c90b15ed72746c0.zip | |
drm/amdgpu: add support to configure MALL for sienna_cichlid (v2)
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid.
v2: drop module option. We need to add UAPI so userspace can
request MALL per buffer.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 18eca0d4dbcc..ae6158456094 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -707,7 +707,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) temp &= 0xFF0FFF; temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | - 0x01000000); + SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); if (!amdgpu_sriov_vf(adev)) { |