diff options
| author | Jun Lei <Jun.Lei@amd.com> | 2019-07-08 21:15:42 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 21:27:26 +0200 |
| commit | 057fc695e934a77bae0c6c7f3be01251774b61cf (patch) | |
| tree | 405f1311da2b64d9faa06c11f6173c024160acfc /drivers/gpu/drm/amd/display/dc/clk_mgr | |
| parent | drm/amd/display: fix mpcc assert condition (diff) | |
| download | linux-057fc695e934a77bae0c6c7f3be01251774b61cf.tar.xz linux-057fc695e934a77bae0c6c7f3be01251774b61cf.zip | |
drm/amd/display: support "dummy pstate"
[why]
Existing support in DC for pstate only accounts for a single latency. This is sufficient when the
variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality.
Newer ASICs violate both existing assumptions. PState support is mandatory of correct ASIC
functionality, but not all latencies have to be supported. Existing code supports a "full p state" which
allows memory clock to change, but is hard for DCN to support (as it requires very large buffers).
New code will now fall back to a "dummy p state" support when "full p state" cannot be support.
This easy p state support should always be allowed.
[how]
Define a new latency in socBB. Add fallback logic to support it. Note DML is also updated to ensure
that fallback will always work.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 3cff4f0518d3..7ff0396956b3 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -201,6 +201,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, } if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { + clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; if (pp_smu && pp_smu->set_pstate_handshake_support) pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); @@ -308,6 +309,7 @@ void dcn2_init_clocks(struct clk_mgr *clk_mgr) memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); // Assumption is that boot state always supports pstate clk_mgr->clks.p_state_change_support = true; + clk_mgr->clks.prev_p_state_change_support = true; } void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) |