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| author | Dave Airlie <airlied@redhat.com> | 2017-10-09 03:21:15 +0200 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2017-10-09 03:21:15 +0200 |
| commit | b9e56e41e0c55c2b2ab5919c5e167faa4200b083 (patch) | |
| tree | 8b580cf1e412a1c7078fe75994d3effeb297bfc3 /drivers/gpu/drm/amd/include | |
| parent | Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux int... (diff) | |
| parent | amdgpu/dc: use kref for dc_state. (diff) | |
| download | linux-b9e56e41e0c55c2b2ab5919c5e167faa4200b083.tar.xz linux-b9e56e41e0c55c2b2ab5919c5e167faa4200b083.zip | |
Merge branch 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux into drm-next
Initial pull request for DC support. We've completed a substantial amount of
the cleanup and restructuring in our TODO. There are a few additional
cleanups that we are continuing to work on, but I don't think there are any
showstoppers remaining. We've tried to maintain most of the history for bisect
purposes. Harry made sure all the commits build. We've enabled DC for vega10
and Raven. Pre-vega10 parts can be enabled via module parameter (amdgpu.dc=1),
but are not enabled by default at this point until we get further testing
upstream.
This code provides atomic modesetting support for DCE8 (CIK), DCE10 (Tonga,
Fiji), DCE11 (CZ, ST, Polaris), DCE12 (vega10), and DCN1 (RV) including
HDMI and DP audio, DP MST, and many other advanced display features.
+
Latest cleanups for DC from you and Harry. Note that there is some
flickering on some older asics with this branch due to a regression in powerplay
that has already been fixed and will be included in my next non-DC pull request
next week.
* 'drm-next-4.15-dc' of git://people.freedesktop.org/~agd5f/linux: (897 commits)
amdgpu/dc: use kref for dc_state.
amdgpu/dc: convert dc_sink to kref.
amdgpu/dc: convert dc_stream_state to kref.
amdgpu/dc: use kref for dc_plane_state.
amdgpu/dc: convert dc_gamma to kref reference counting.
amdgpu/dc: convert dc_transfer to use a kref.
amdgpu/dc: kill a bunch of dead code.
amdgpu/dc: set a bunch of functions to static.
amdgpu/dc: kill some deadcode in dc core.
amdgpu/dc: fix indentation on a couple of returns.
amdgpu/dm: don't use after free.
amdgpu/dc: kfree already checks for NULL.
amdgpu/dc: fix a bunch of misc whitespace.
amdgpu/dc: drop hw_sequencer_types.h
amdgpu/dc: drop dce110_types.h
amdgpu/dc: use kernel ilog2 for log_2.
amdgpu/dc: don't memset after kzalloc.
amdgpu/dc: inline dal grph object id functions.
amdgpu/dc: inline dml_round_to_multiple
amdgpu/dc: rename bios get_image symbol to something more searchable.
...
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h | 5 |
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h index b39fb6821faa..4ccf9681c45d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h @@ -2283,6 +2283,10 @@ #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 #define mmDCHUBBUB_SPARE 0x0534 #define mmDCHUBBUB_SPARE_BASE_IDX 2 +#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053a +#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053b +#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec @@ -10361,6 +10365,8 @@ #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 #define mmDCIO_WRCMD_DELAY 0x287e #define mmDCIO_WRCMD_DELAY_BASE_IDX 2 +#define mmDC_PINSTRAPS 0x2880 +#define mmDC_PINSTRAPS_BASE_IDX 2 #define mmDC_DVODATA_CONFIG 0x2882 #define mmDC_DVODATA_CONFIG_BASE_IDX 2 #define mmLVTMA_PWRSEQ_CNTL 0x2883 diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h index 1e98ce86ed19..b28d4b64c05d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h @@ -9361,12 +9361,14 @@ #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 #define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL //HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa #define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L #define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L @@ -39956,6 +39958,9 @@ #define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L #define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L #define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L //DC_DVODATA_CONFIG #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 |