diff options
| author | Marco Felsch <m.felsch@pengutronix.de> | 2022-08-26 21:07:28 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2022-09-23 22:04:14 +0200 |
| commit | 4bce244272513ebb4d13c570e9fbca28497015b2 (patch) | |
| tree | 9d4817fdde093ffe9665d3cc548934996f5c9898 /drivers/gpu/drm/etnaviv | |
| parent | drm/etnaviv: don't truncate physical page address (diff) | |
| download | linux-4bce244272513ebb4d13c570e9fbca28497015b2.tar.xz linux-4bce244272513ebb4d13c570e9fbca28497015b2.zip | |
drm/etnaviv: disable tx clock gating for GC7000 rev6203
The i.MX8MN SoC errata sheet mentions ERR050226: "GPU: Texture L2 Cache
idle signal may incorrectly clock gate the texture engine in GPU".
The workaround is to disable the corresponding clock gatings.
While on it move the clock gating check for rev6202 into the same check
to bundle them.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'drivers/gpu/drm/etnaviv')
| -rw-r--r-- | drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index ed2f9c8f288c..51320eeebfcf 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -623,14 +623,15 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) /* Disable TX clock gating on affected core revisions. */ if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || - etnaviv_is_model_rev(gpu, GC2000, 0x5108)) + etnaviv_is_model_rev(gpu, GC2000, 0x5108) || + etnaviv_is_model_rev(gpu, GC2000, 0x6202) || + etnaviv_is_model_rev(gpu, GC2000, 0x6203)) pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; - /* Disable SE, RA and TX clock gating on affected core revisions. */ + /* Disable SE and RA clock gating on affected core revisions. */ if (etnaviv_is_model_rev(gpu, GC7000, 0x6202)) pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | - VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA | - VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; + VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA; pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; |