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authorVille Syrjälä <ville.syrjala@linux.intel.com>2023-02-13 23:52:50 +0100
committerVille Syrjälä <ville.syrjala@linux.intel.com>2023-02-17 22:25:15 +0100
commit3eb08ea58e5717cf758b9eff6d9604aa3525ab94 (patch)
treef3dbad3b13d793f0fb6924dce01595c19298cbde /drivers/gpu/drm/i915/display/intel_lvds.c
parentdrm/i915: Give CPU transcoder timing registers TRANS_ prefix (diff)
downloadlinux-3eb08ea58e5717cf758b9eff6d9604aa3525ab94.tar.xz
linux-3eb08ea58e5717cf758b9eff6d9604aa3525ab94.zip
drm/i915: s/PIPECONF/TRANSCONF/
Rename PIPECONF to TRANSCONF to make it clear what it actually applies to. While the usual convention is to pick the earliers name I think in this case it's more clear to use the later name. Especially as even the register offset is in the wrong range (0x70000 vs. 0x60000) and thus makes it look like this is per-pipe. There is one place in gvt that's doing something with TRANSCONF while iterating with for_each_pipe(). So that might not be doing the right thing for TRANSCODER_EDP, dunno. Not knowing what it does I left it as is to avoid breakage. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_lvds.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_lvds.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 1df67457f10a..a504b3a7fbd5 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -286,7 +286,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
/*
* Set the dithering flag on LVDS as needed, note that there is no
* special lvds dither control bit on pch-split platforms, dithering is
- * only controlled through the PIPECONF reg.
+ * only controlled through the TRANSCONF reg.
*/
if (DISPLAY_VER(i915) == 4) {
/*