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authorVille Syrjälä <ville.syrjala@linux.intel.com>2021-05-06 09:38:36 +0200
committerVille Syrjälä <ville.syrjala@linux.intel.com>2021-05-07 07:09:54 +0200
commit7c653e15e2ba4c476ea9aa1f5ddf14ca3ccacc17 (patch)
treeea66f87730bca2310c8238a6783b392fea46ef93 /drivers/gpu/drm/i915/display/skl_universal_plane.c
parentdrm/i915: Nuke display error state (diff)
downloadlinux-7c653e15e2ba4c476ea9aa1f5ddf14ca3ccacc17.tar.xz
linux-7c653e15e2ba4c476ea9aa1f5ddf14ca3ccacc17.zip
drm/i915: Reorder skl+ scaler vs. plane updates
When scanning out NV12 if we at any time have the plane enabled while the scaler is disabled we get a pretty catastrophic underrun. Let's reorder the operations so that we try to avoid that happening even if our vblank evade fails and the scaler enable/disable and the plane enable/disable get latched during two diffent frames. This takes care of the most common cases. I suppose there is still at least a theoretical possibility of hitting this if one plane takes the scaler away from another plane before the second plane had a chance to set up another scaler for its use. But that is starting to get a bit complicated, especially since the plane commit order already has to be carefully sequenced to avoid any dbuf overlaps. So plugging this 100% may prove somewhat hard... Cc: Cooper Chiou <cooper.chiou@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210506073836.14848-1-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/skl_universal_plane.c')
-rw-r--r--drivers/gpu/drm/i915/display/skl_universal_plane.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0d34a5ad4e2b..6ad85d7cb219 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1033,6 +1033,14 @@ skl_program_plane(struct intel_plane *plane,
intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
/*
+ * Enable the scaler before the plane so that we don't
+ * get a catastrophic underrun even if the two operations
+ * end up happening in two different frames.
+ */
+ if (plane_state->scaler_id >= 0)
+ skl_program_plane_scaler(plane, crtc_state, plane_state);
+
+ /*
* The control register self-arms if the plane was previously
* disabled. Try to make the plane enable atomic by writing
* the control register just before the surface register.
@@ -1041,9 +1049,6 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
intel_plane_ggtt_offset(plane_state) + surf_addr);
- if (plane_state->scaler_id >= 0)
- skl_program_plane_scaler(plane, crtc_state, plane_state);
-
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}