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authorBen Widawsky <ben@bwidawsk.net>2012-09-24 17:55:51 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-11 23:51:10 +0100
commit8f2c59f0aa3acefbd26443860245c014fa64549b (patch)
tree2e73d22d3d9d3aef37d91868644790511e04a461 /drivers/gpu/drm/i915/i915_gem_gtt.c
parentdrm/i915: No LLC_MLC for HSW. (diff)
downloadlinux-8f2c59f0aa3acefbd26443860245c014fa64549b.tar.xz
linux-8f2c59f0aa3acefbd26443860245c014fa64549b.zip
drm/i915: Add dev to ppgtt
Some subsequent commits will need to know what generation we're running on to do different pte encoding for the ppgtt. Since it's not much hassle or overhead to store it in the ppgtt structure, do that. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c040aad0cca6..ed0fe15a41f4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -77,6 +77,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
if (!ppgtt)
return ret;
+ ppgtt->dev = dev;
ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
GFP_KERNEL);
@@ -218,7 +219,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
switch (cache_level) {
case I915_CACHE_LLC_MLC:
/* Haswell doesn't set L3 this way */
- if (IS_HASWELL(obj->base.dev))
+ if (IS_HASWELL(ppgtt->dev))
pte_flags |= GEN6_PTE_CACHE_LLC;
else
pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
@@ -227,7 +228,7 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
pte_flags |= GEN6_PTE_CACHE_LLC;
break;
case I915_CACHE_NONE:
- if (IS_HASWELL(obj->base.dev))
+ if (IS_HASWELL(ppgtt->dev))
pte_flags |= HSW_PTE_UNCACHED;
else
pte_flags |= GEN6_PTE_UNCACHED;