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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-03-14 01:30:06 +0100 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 00:29:56 +0100 |
| commit | 911aeb0f61b8cb9b903105d2e585e80baadb513b (patch) | |
| tree | b11ee1a227bc23bddf6f252ce551166d99612529 /drivers/gpu/drm/xe/xe_tuning.c | |
| parent | drm/xe: Add PVC engine workarounds (diff) | |
| download | linux-911aeb0f61b8cb9b903105d2e585e80baadb513b.tar.xz linux-911aeb0f61b8cb9b903105d2e585e80baadb513b.zip | |
drm/xe: Add missing DG2 gt workarounds and tunings
Synchronize with i915 the DG2 gt workarounds as of
commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w access
order").
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230314003012.2600353-9-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_tuning.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_tuning.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c index 2861a014c85c..47b27dccb385 100644 --- a/drivers/gpu/drm/xe/xe_tuning.c +++ b/drivers/gpu/drm/xe/xe_tuning.c @@ -16,6 +16,10 @@ #define MCR_REG(x) _XE_RTP_MCR_REG(x) static const struct xe_rtp_entry gt_tunings[] = { + { XE_RTP_NAME("Tuning: Blend Fill Caching Optimization Disable"), + XE_RTP_RULES(PLATFORM(DG2)), + XE_RTP_ACTIONS(SET(XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS)) + }, { XE_RTP_NAME("Tuning: 32B Access Enable"), XE_RTP_RULES(PLATFORM(DG2)), XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS)) |