diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-06-08 22:30:49 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-06-13 18:04:25 +0200 |
| commit | a43d92812077b15c8e3bfdf80dc9d8596b503c60 (patch) | |
| tree | cb4c8decf5d94797efcb5497de6bc6554c537f8d /drivers/gpu/drm | |
| parent | drm/i915/dsi: Split icl+ D-PHY vs. DSI timing steps (diff) | |
| download | linux-a43d92812077b15c8e3bfdf80dc9d8596b503c60.tar.xz linux-a43d92812077b15c8e3bfdf80dc9d8596b503c60.zip | |
drm/i915/dsi: Gate DSI clocks earlier
The clock gating step is in the wrong spot compared to the
TGL+ bspec sequence. Move it the right place. Windows also
seems to use the TGL+ order here always.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230608203057.23759-6-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/display/icl_dsi.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 6d60197cc9f1..973215bec3c1 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1110,6 +1110,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, /* enable DDI buffer */ gen11_dsi_enable_ddi_buffer(encoder); + gen11_dsi_gate_clocks(encoder); + gen11_dsi_setup_timings(encoder, crtc_state); /* Since transcoder is configured to take events from GPIO */ @@ -1120,9 +1122,6 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, /* Step (4h, 4i, 4j, 4k): Configure transcoder */ gen11_dsi_configure_transcoder(encoder, crtc_state); - - /* Step 4l: Gate DDI clocks */ - gen11_dsi_gate_clocks(encoder); } static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) |