diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2021-07-17 07:14:25 +0200 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-07-21 19:46:43 +0200 |
| commit | efa894a50296ae1e07983eebd2c4ebc2b4d17a1a (patch) | |
| tree | c58458e6b585bde630877ae3f5f6b20f4aa3de8f /drivers/gpu | |
| parent | drm/i915/rkl: Wa_1409767108 also applies to RKL (diff) | |
| download | linux-efa894a50296ae1e07983eebd2c4ebc2b4d17a1a.tar.xz linux-efa894a50296ae1e07983eebd2c4ebc2b4d17a1a.zip | |
drm/i915/rkl: Wa_1408330847 no longer applies to RKL
RKL doesn't have PSR2 support, so PSR2-related workarounds no longer
apply.
Bspec: 53273
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210717051426.4120328-7-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7218a5f6a1b3..13d31247d2f3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -594,9 +594,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_SU_SDP_SCANLINE; if (intel_dp->psr.psr2_sel_fetch_enabled) { - /* WA 1408330847 */ - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) || - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) + /* Wa_1408330847 */ + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, DIS_RAM_BYPASS_PSR2_MAN_TRACK); @@ -1345,10 +1344,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_psr_exit(intel_dp); intel_psr_wait_exit_locked(intel_dp); - /* WA 1408330847 */ + /* Wa_1408330847 */ if (intel_dp->psr.psr2_sel_fetch_enabled && - (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) || - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))) + IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); |