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| author | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2018-03-01 10:14:24 +0100 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2018-03-01 10:14:24 +0100 |
| commit | bba73071b6f71be0a101658d7c13866e30b264a6 (patch) | |
| tree | 2a0ea1fc5fd975f1c2e9e50de5bb3cb2cb3cb5f7 /drivers/media/platform/davinci/vpss.c | |
| parent | drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array (diff) | |
| parent | Merge tag 'drm-intel-next-2018-02-21' of git://anongit.freedesktop.org/drm/dr... (diff) | |
| download | linux-bba73071b6f71be0a101658d7c13866e30b264a6.tar.xz linux-bba73071b6f71be0a101658d7c13866e30b264a6.zip | |
Merge drm-next into drm-intel-next-queued (this time for real)
To pull in the HDCP changes, especially wait_for changes to drm/i915
that Chris wants to build on top of.
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/media/platform/davinci/vpss.c')
| -rw-r--r-- | drivers/media/platform/davinci/vpss.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/media/platform/davinci/vpss.c b/drivers/media/platform/davinci/vpss.c index f2d27b932999..b73886519f4f 100644 --- a/drivers/media/platform/davinci/vpss.c +++ b/drivers/media/platform/davinci/vpss.c @@ -59,9 +59,9 @@ MODULE_AUTHOR("Texas Instruments"); #define DM365_ISP5_INTSEL1 0x10 #define DM365_ISP5_INTSEL2 0x14 #define DM365_ISP5_INTSEL3 0x18 -#define DM365_ISP5_CCDCMUX 0x20 -#define DM365_ISP5_PG_FRAME_SIZE 0x28 -#define DM365_VPBE_CLK_CTRL 0x00 +#define DM365_ISP5_CCDCMUX 0x20 +#define DM365_ISP5_PG_FRAME_SIZE 0x28 +#define DM365_VPBE_CLK_CTRL 0x00 #define VPSS_CLK_CTRL 0x01c40044 #define VPSS_CLK_CTRL_VENCCLKEN BIT(3) @@ -78,8 +78,8 @@ MODULE_AUTHOR("Texas Instruments"); #define DM365_ISP5_INTSEL3_DEFAULT 0x00000015 /* masks and shifts for DM365*/ -#define DM365_CCDC_PG_VD_POL_SHIFT 0 -#define DM365_CCDC_PG_HD_POL_SHIFT 1 +#define DM365_CCDC_PG_VD_POL_SHIFT 0 +#define DM365_CCDC_PG_HD_POL_SHIFT 1 #define CCD_SRC_SEL_MASK (BIT_MASK(5) | BIT_MASK(4)) #define CCD_SRC_SEL_SHIFT 4 |