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author | Bin Meng <bmeng.cn@gmail.com> | 2017-09-11 11:41:56 +0200 |
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committer | Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2017-10-11 09:46:04 +0200 |
commit | aecf59e90a494f5d439415ce8d50064f6c644615 (patch) | |
tree | 73936712745f4efc85c74ab2cc5723a940af55d0 /drivers/mtd/spi-nor | |
parent | spi-nor: intel-spi: Use SW sequencer for BYT/LPT (diff) | |
download | linux-aecf59e90a494f5d439415ce8d50064f6c644615.tar.xz linux-aecf59e90a494f5d439415ce8d50064f6c644615.zip |
spi-nor: intel-spi: Remove 'Atomic Cycle Sequence' in intel_spi_write()
So far intel_spi_write() uses the HW sequencer to do the write. But
the HW sequencer register HSFSTS_CTL does not have such a field for
'Atomic Cycle Sequence', remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Diffstat (limited to 'drivers/mtd/spi-nor')
-rw-r--r-- | drivers/mtd/spi-nor/intel-spi.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c index d0237fe5779c..757b9f14fd73 100644 --- a/drivers/mtd/spi-nor/intel-spi.c +++ b/drivers/mtd/spi-nor/intel-spi.c @@ -572,11 +572,6 @@ static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len, val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; val |= HSFSTS_CTL_FCYCLE_WRITE; - - /* Write enable */ - if (ispi->preopcodes[1] == SPINOR_OP_WREN) - val |= SSFSTS_CTL_SPOP; - val |= SSFSTS_CTL_ACS; writel(val, ispi->base + HSFSTS_CTL); ret = intel_spi_write_block(ispi, write_buf, block_size); |