diff options
| author | Carolyn Wyborny <carolyn.wyborny@intel.com> | 2012-10-23 14:54:33 +0200 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2012-12-01 12:30:20 +0100 |
| commit | daf56e406a94675d454f996cab56c3d0b0a0d8a6 (patch) | |
| tree | f8a4e6ab413490c02d3e4966d3736d65346e4c04 /drivers/net/ethernet/intel/igb/e1000_defines.h | |
| parent | igb: Unset sigdetect for SERDES loopback on 82580 and i350 (diff) | |
| download | linux-daf56e406a94675d454f996cab56c3d0b0a0d8a6.tar.xz linux-daf56e406a94675d454f996cab56c3d0b0a0d8a6.zip | |
igb: Fix SerDes autoneg flow control.
This patch enables flow control to be set in SerDes autoneg mode. This is
done the way it is done for copper, but relies on a different set of register/bit
checks since this is all done within the MAC registers.
Signed-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/igb/e1000_defines.h')
| -rw-r--r-- | drivers/net/ethernet/intel/igb/e1000_defines.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h index 198d14848820..45dce06eff26 100644 --- a/drivers/net/ethernet/intel/igb/e1000_defines.h +++ b/drivers/net/ethernet/intel/igb/e1000_defines.h @@ -431,6 +431,10 @@ #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 #define FLOW_CONTROL_TYPE 0x8808 +/* Transmit Config Word */ +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ + /* 802.1q VLAN Packet Size */ #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ @@ -539,6 +543,9 @@ /* mPHY Near End Digital Loopback Override Bit */ #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 +#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 +#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 + /* PHY Control Register */ #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |