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| author | Marcel Ziswiler <marcel@ziswiler.com> | 2020-01-07 09:14:02 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-01-10 18:29:39 +0100 |
| commit | 21a92676e1fe292acb077b13106b08c22ed36b14 (patch) | |
| tree | efa0583ce9d6c6c17f25ff8a75f06d783c5e6ec2 /drivers/pci/controller/pci-tegra.c | |
| parent | PCI: tegra: Fix return value check of pm_runtime_get_sync() (diff) | |
| download | linux-21a92676e1fe292acb077b13106b08c22ed36b14.tar.xz linux-21a92676e1fe292acb077b13106b08c22ed36b14.zip | |
PCI: tegra: Fix afi_pex2_ctrl reg offset for Tegra30
Fix AFI_PEX2_CTRL reg offset for Tegra30 by moving it from the Tegra20
SoC struct where it erroneously got added. This fixes the AFI_PEX2_CTRL
reg offset being uninitialised subsequently failing to bring up the
third PCIe port.
Fixes: adb2653b3d2e ("PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct")
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/pci/controller/pci-tegra.c')
| -rw-r--r-- | drivers/pci/controller/pci-tegra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 090b632965e2..ac93f5a0398e 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -2499,7 +2499,6 @@ static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .ports = tegra20_pcie_ports, .msi_base_shift = 0, - .afi_pex2_ctrl = 0x128, .pads_pll_ctl = PADS_PLL_CTL_TEGRA20, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10, .pads_refclk_cfg0 = 0xfa5cfa5c, @@ -2528,6 +2527,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .num_ports = 3, .ports = tegra30_pcie_ports, .msi_base_shift = 8, + .afi_pex2_ctrl = 0x128, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, .pads_refclk_cfg0 = 0xfa5cfa5c, |