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| author | Emil Renner Berthing <kernel@esmil.dk> | 2023-04-01 13:19:21 +0200 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-04-05 16:43:53 +0200 |
| commit | 1ec3d20e4e2fef33c618b2ef550cbf3b4728e4cd (patch) | |
| tree | 185112a160b4990d098cb7702606529a65a1ad2d /drivers/reset/starfive/reset-starfive-jh71x0.h | |
| parent | reset: Create subdirectory for StarFive drivers (diff) | |
| download | linux-1ec3d20e4e2fef33c618b2ef550cbf3b4728e4cd.tar.xz linux-1ec3d20e4e2fef33c618b2ef550cbf3b4728e4cd.zip | |
reset: starfive: Factor out common JH71X0 reset code
The StarFive JH7100 SoC has additional reset controllers for audio and
video, but the registers follow the same structure. On the JH7110 the
reset registers don't get their own memory range, but instead follow the
clock control registers. The registers still follow the same structure
though, so let's factor out the common code to handle all these cases.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'drivers/reset/starfive/reset-starfive-jh71x0.h')
| -rw-r--r-- | drivers/reset/starfive/reset-starfive-jh71x0.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h new file mode 100644 index 000000000000..318d7a0e096a --- /dev/null +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> + */ + +#ifndef __RESET_STARFIVE_JH71X0_H +#define __RESET_STARFIVE_JH71X0_H + +int jh7100_reset_probe(struct platform_device *pdev); + +#endif /* __RESET_STARFIVE_JH71X0_H */ |