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authorPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>2024-10-04 04:18:50 +0200
committerVinod Koul <vkoul@kernel.org>2024-10-10 14:13:55 +0200
commitcbcb7edd099aee3f001c008fb8bbb1c0d2b7154c (patch)
tree2bbafe28b146a1b2b09bd8337a683ef1177c9690 /drivers/soundwire
parentsoundwire: mipi-disco: add support for DP0/DPn 'lane-list' property (diff)
downloadlinux-cbcb7edd099aee3f001c008fb8bbb1c0d2b7154c.tar.xz
linux-cbcb7edd099aee3f001c008fb8bbb1c0d2b7154c.zip
soundwire: intel_auxdevice: add kernel parameter for mclk divider
Add a kernel parameter to work-around discrepancies between hardware and platform firmware, it's not unusual to see e.g. 38.4MHz listed in _DSD properties as the SoundWire clock source, but the hardware may be based on a 19.2 MHz mclk source. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20241004021850.9758-1-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/soundwire')
-rw-r--r--drivers/soundwire/intel_auxdevice.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/soundwire/intel_auxdevice.c b/drivers/soundwire/intel_auxdevice.c
index ae689d5d1ab9..599954d92752 100644
--- a/drivers/soundwire/intel_auxdevice.c
+++ b/drivers/soundwire/intel_auxdevice.c
@@ -41,6 +41,10 @@ static int md_flags;
module_param_named(sdw_md_flags, md_flags, int, 0444);
MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
+static int mclk_divider;
+module_param_named(sdw_mclk_divider, mclk_divider, int, 0444);
+MODULE_PARM_DESC(sdw_mclk_divider, "SoundWire Intel mclk divider");
+
struct wake_capable_part {
const u16 mfg_id;
const u16 part_id;
@@ -142,8 +146,12 @@ static int sdw_master_read_intel_prop(struct sdw_bus *bus)
"intel-sdw-ip-clock",
&prop->mclk_freq);
- /* the values reported by BIOS are the 2x clock, not the bus clock */
- prop->mclk_freq /= 2;
+ if (mclk_divider)
+ /* use kernel parameter for BIOS or board work-arounds */
+ prop->mclk_freq /= mclk_divider;
+ else
+ /* the values reported by BIOS are the 2x clock, not the bus clock */
+ prop->mclk_freq /= 2;
fwnode_property_read_u32(link,
"intel-quirk-mask",