diff options
| author | Alvin Lee <Alvin.Lee2@amd.com> | 2022-05-19 20:03:09 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-25 23:17:43 +0200 |
| commit | 493af96d61b1361a44d016057e0fc6e5d4c92fc7 (patch) | |
| tree | 183a27dd32032e459adf9bc81a178c8f9864e242 /drivers | |
| parent | drm/amd/display: Add reinstate dram in the FPO logic (diff) | |
| download | linux-493af96d61b1361a44d016057e0fc6e5d4c92fc7.tar.xz linux-493af96d61b1361a44d016057e0fc6e5d4c92fc7.zip | |
drm/amd/display: Update DCN32 and DCN321 SR latencies
Update worst case SR latencies according to values measured by hardware
team.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 01e272f0bb05..66453546e24f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -121,8 +121,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { }, }, .num_states = 1, - .sr_exit_time_us = 5.20, - .sr_enter_plus_exit_time_us = 9.60, + .sr_exit_time_us = 20.16, + .sr_enter_plus_exit_time_us = 27.13, .sr_exit_z8_time_us = 285.0, .sr_enter_plus_exit_z8_time_us = 320, .writeback_latency_us = 12.0, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c index 6e72336b7975..84b4b00f29cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c @@ -119,8 +119,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = { }, }, .num_states = 1, - .sr_exit_time_us = 5.20, - .sr_enter_plus_exit_time_us = 9.60, + .sr_exit_time_us = 12.36, + .sr_enter_plus_exit_time_us = 16.72, .sr_exit_z8_time_us = 285.0, .sr_enter_plus_exit_z8_time_us = 320, .writeback_latency_us = 12.0, |