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| author | Uwe Kleine-König <u.kleine-koenig@baylibre.com> | 2024-11-04 11:19:04 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2024-12-07 18:13:25 +0100 |
| commit | 4be339af334c283a1a1af3cb28e7e448a0aa8a7c (patch) | |
| tree | e6a9ca3927b78abf033c2c206a4575d98bd0c1a9 /drivers | |
| parent | staging: iio: ad9832: Correct phase range check (diff) | |
| download | linux-4be339af334c283a1a1af3cb28e7e448a0aa8a7c.tar.xz linux-4be339af334c283a1a1af3cb28e7e448a0aa8a7c.zip | |
iio: adc: ad7124: Disable all channels at probe time
When during a measurement two channels are enabled, two measurements are
done that are reported sequencially in the DATA register. As the code
triggered by reading one of the sysfs properties expects that only one
channel is enabled it only reads the first data set which might or might
not belong to the intended channel.
To prevent this situation disable all channels during probe. This fixes
a problem in practise because the reset default for channel 0 is
enabled. So all measurements before the first measurement on channel 0
(which disables channel 0 at the end) might report wrong values.
Fixes: 7b8d045e497a ("iio: adc: ad7124: allow more than 8 channels")
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://patch.msgid.link/20241104101905.845737-2-u.kleine-koenig@baylibre.com
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/iio/adc/ad7124.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 7314fb32bdec..3d678c420cbf 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -917,6 +917,9 @@ static int ad7124_setup(struct ad7124_state *st) * set all channels to this default value. */ ad7124_set_channel_odr(st, i, 10); + + /* Disable all channels to prevent unintended conversions. */ + ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, 0); } ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); |