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| author | Bjorn Andersson <andersson@kernel.org> | 2024-08-16 00:05:22 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-08-16 00:05:22 +0200 |
| commit | 2b148bf6030c31ccf0813044f00d911cb47229a0 (patch) | |
| tree | eb7c7acc48ac2da6c2fb7e485b265abf12e6b93f /include/dt-bindings | |
| parent | clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks (diff) | |
| parent | dt-bindings: interconnect: Add Qualcomm IPQ5332 support (diff) | |
| download | linux-2b148bf6030c31ccf0813044f00d911cb47229a0.tar.xz linux-2b148bf6030c31ccf0813044f00d911cb47229a0.zip | |
Merge branch '20240730054817.1915652-2-quic_varada@quicinc.com' into clk-for-6.12
Merge IPQ5332 interconnect binding additions through topic branchs to
allow making the constants available in DeviceTree branch as well.
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,ipq5332.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/include/dt-bindings/interconnect/qcom,ipq5332.h b/include/dt-bindings/interconnect/qcom,ipq5332.h new file mode 100644 index 000000000000..16475bb07a48 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,ipq5332.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef INTERCONNECT_QCOM_IPQ5332_H +#define INTERCONNECT_QCOM_IPQ5332_H + +#define MASTER_SNOC_PCIE3_1_M 0 +#define SLAVE_SNOC_PCIE3_1_M 1 +#define MASTER_ANOC_PCIE3_1_S 2 +#define SLAVE_ANOC_PCIE3_1_S 3 +#define MASTER_SNOC_PCIE3_2_M 4 +#define SLAVE_SNOC_PCIE3_2_M 5 +#define MASTER_ANOC_PCIE3_2_S 6 +#define SLAVE_ANOC_PCIE3_2_S 7 +#define MASTER_SNOC_USB 8 +#define SLAVE_SNOC_USB 9 +#define MASTER_NSSNOC_NSSCC 10 +#define SLAVE_NSSNOC_NSSCC 11 +#define MASTER_NSSNOC_SNOC_0 12 +#define SLAVE_NSSNOC_SNOC_0 13 +#define MASTER_NSSNOC_SNOC_1 14 +#define SLAVE_NSSNOC_SNOC_1 15 +#define MASTER_NSSNOC_ATB 16 +#define SLAVE_NSSNOC_ATB 17 +#define MASTER_NSSNOC_PCNOC_1 18 +#define SLAVE_NSSNOC_PCNOC_1 19 +#define MASTER_NSSNOC_QOSGEN_REF 20 +#define SLAVE_NSSNOC_QOSGEN_REF 21 +#define MASTER_NSSNOC_TIMEOUT_REF 22 +#define SLAVE_NSSNOC_TIMEOUT_REF 23 +#define MASTER_NSSNOC_XO_DCD 24 +#define SLAVE_NSSNOC_XO_DCD 25 + +#define MASTER_NSSNOC_PPE 0 +#define SLAVE_NSSNOC_PPE 1 +#define MASTER_NSSNOC_PPE_CFG 2 +#define SLAVE_NSSNOC_PPE_CFG 3 +#define MASTER_NSSNOC_NSS_CSR 4 +#define SLAVE_NSSNOC_NSS_CSR 5 +#define MASTER_NSSNOC_CE_APB 6 +#define SLAVE_NSSNOC_CE_APB 7 +#define MASTER_NSSNOC_CE_AXI 8 +#define SLAVE_NSSNOC_CE_AXI 9 + +#define MASTER_CNOC_AHB 0 +#define SLAVE_CNOC_AHB 1 + +#endif /* INTERCONNECT_QCOM_IPQ5332_H */ |