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| author | Jason Gunthorpe <jgg@nvidia.com> | 2024-08-27 15:32:25 +0200 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2024-08-28 14:11:29 +0200 |
| commit | 34cd19288161313b6ba24004206ab6a64fdef7c5 (patch) | |
| tree | f83e4dc97edda3e90ddf03d6129f3a458d28c0e2 /include/uapi/rdma | |
| parent | RDMA/efa: Add support for node guid (diff) | |
| parent | RDMA/bnxt_re: Enable variable size WQEs for user space applications (diff) | |
| download | linux-34cd19288161313b6ba24004206ab6a64fdef7c5.tar.xz linux-34cd19288161313b6ba24004206ab6a64fdef7c5.zip | |
Merge branch 'bnxt_re_variable_wqes' into rdma.git for-next
Selvin Xavier says:
=============
Enable the Variable size Work Queue entry support for Gen P7
adapters. This would help in the better utilization of the queue memory
and pci bandwidth due to the smaller send queue Work entries.
=============
Based on v6.11-rc5 for dependencies.
* bnxt_re_variable_wqes: (829 commits)
RDMA/bnxt_re: Enable variable size WQEs for user space applications
RDMA/bnxt_re: Handle variable WQE support for user applications
RDMA/bnxt_re: Fix the table size for PSN/MSN entries
RDMA/bnxt_re: Get the WQE index from slot index while completing the WQEs
RDMA/bnxt_re: Add support for Variable WQE in Genp7 adapters
Linux 6.11-rc5
...
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'include/uapi/rdma')
| -rw-r--r-- | include/uapi/rdma/bnxt_re-abi.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/include/uapi/rdma/bnxt_re-abi.h b/include/uapi/rdma/bnxt_re-abi.h index e61104f35d73..6821002931c8 100644 --- a/include/uapi/rdma/bnxt_re-abi.h +++ b/include/uapi/rdma/bnxt_re-abi.h @@ -66,6 +66,7 @@ enum bnxt_re_wqe_mode { enum { BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT = 0x01, + BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT = 0x02, }; struct bnxt_re_uctx_req { @@ -118,10 +119,16 @@ struct bnxt_re_resize_cq_req { __aligned_u64 cq_va; }; +enum bnxt_re_qp_mask { + BNXT_RE_QP_REQ_MASK_VAR_WQE_SQ_SLOTS = 0x1, +}; + struct bnxt_re_qp_req { __aligned_u64 qpsva; __aligned_u64 qprva; __aligned_u64 qp_handle; + __aligned_u64 comp_mask; + __u32 sq_slots; }; struct bnxt_re_qp_resp { |