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| author | Vandita Kulkarni <vandita.kulkarni@intel.com> | 2019-07-11 19:31:04 +0200 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2019-07-12 01:31:12 +0200 |
| commit | 68ff39c3f8c01b1e640d111abdcf814804a6b236 (patch) | |
| tree | a891f805842409034fedcf2615a228f79376dd60 /kernel/hung_task.c | |
| parent | drm/i915/tgl: Add power well to support 4th pipe (diff) | |
| download | linux-68ff39c3f8c01b1e640d111abdcf814804a6b236.tar.xz linux-68ff39c3f8c01b1e640d111abdcf814804a6b236.zip | |
drm/i915/tgl: Add new pll ids
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-11-lucas.demarchi@intel.com
Diffstat (limited to 'kernel/hung_task.c')
0 files changed, 0 insertions, 0 deletions