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-rw-r--r--arch/arm/boot/dts/am3517.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts6
-rw-r--r--arch/arm/boot/dts/omap3-tao3530.dtsi6
-rw-r--r--arch/arm/boot/dts/omap3.dtsi57
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c61
5 files changed, 64 insertions, 70 deletions
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index dc8927f14b6c..9cb88f7700bb 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -10,6 +10,10 @@
#include "omap3.dtsi"
+/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
+/delete-node/ &aes1_target;
+/delete-node/ &aes2_target;
+
/ {
aliases {
serial3 = &uart4;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 4089d97405c9..0905b6849e58 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -19,7 +19,11 @@
* but it is not widely used and to prevent kernel crash rather AES is disabled.
* There is also no runtime detection code if AES is disabled in L3 firewall...
*/
-&aes {
+&aes1_target {
+ status = "disabled";
+};
+
+&aes2_target {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index f24e2326cfa7..59e375dfadf1 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -8,7 +8,11 @@
#include "omap34xx.dtsi"
/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
+&aes1_target {
+ status = "disabled";
+};
+
+&aes2_target {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1296d0643943..6e874ed64009 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -157,13 +157,56 @@
};
};
- aes: aes@480c5000 {
- compatible = "ti,omap3-aes";
- ti,hwmods = "aes";
- reg = <0x480c5000 0x50>;
- interrupts = <0>;
- dmas = <&sdma 65 &sdma 66>;
- dma-names = "tx", "rx";
+ aes1_target: target-module@480a6000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x480a6044 0x4>,
+ <0x480a6048 0x4>,
+ <0x480a604c 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&aes1_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x480a6000 0x2000>;
+
+ aes1: aes1@0 {
+ compatible = "ti,omap3-aes";
+ reg = <0 0x50>;
+ interrupts = <0>;
+ dmas = <&sdma 9 &sdma 10>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ aes2_target: target-module@480c5000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x480c5044 0x4>,
+ <0x480c5048 0x4>,
+ <0x480c504c 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&aes2_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x480c5000 0x2000>;
+
+ aes2: aes2@0 {
+ compatible = "ti,omap3-aes";
+ reg = <0 0x50>;
+ interrupts = <0>;
+ dmas = <&sdma 65 &sdma 66>;
+ dma-names = "tx", "rx";
+ };
};
prm: prm@48306000 {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ca02f91237e3..b6c7d98a9eff 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2342,44 +2342,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_core -> AES */
-static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
- .rev_offs = 0x44,
- .sysc_offs = 0x48,
- .syss_offs = 0x4c,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap3xxx_aes_sysc_fields,
-};
-
-static struct omap_hwmod_class omap3xxx_aes_class = {
- .name = "aes",
- .sysc = &omap3_aes_sysc,
-};
-
-
-static struct omap_hwmod omap3xxx_aes_hwmod = {
- .name = "aes",
- .main_clk = "aes2_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
- },
- },
- .class = &omap3xxx_aes_class,
-};
-
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_aes_hwmod,
- .clk = "aes2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/*
* 'ssi' class
* synchronous serial interface (multichannel and full-duplex serial if)
@@ -2473,20 +2435,11 @@ static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
NULL,
};
-static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_core__aes,
- NULL,
-};
-
static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham,
NULL
};
-static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_core__aes,
- NULL
-};
/*
* Apparently the SHA/MD5 and AES accelerator IP blocks are
@@ -2501,11 +2454,6 @@ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
NULL
};
-static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
- /* &omap3xxx_l4_core__aes, */
- NULL,
-};
-
/* 3430ES1-only hwmod links */
static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
&omap3430es1_dss__l3,
@@ -2641,7 +2589,6 @@ int __init omap3xxx_hwmod_init(void)
{
int r;
struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
- struct omap_hwmod_ocp_if **h_aes = NULL;
struct device_node *bus;
unsigned int rev;
@@ -2664,16 +2611,13 @@ int __init omap3xxx_hwmod_init(void)
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmod_ocp_ifs;
h_sham = omap34xx_sham_hwmod_ocp_ifs;
- h_aes = omap34xx_aes_hwmod_ocp_ifs;
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
h = am35xx_hwmod_ocp_ifs;
h_sham = am35xx_sham_hwmod_ocp_ifs;
- h_aes = am35xx_aes_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmod_ocp_ifs;
h_sham = omap36xx_sham_hwmod_ocp_ifs;
- h_aes = omap36xx_aes_hwmod_ocp_ifs;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
@@ -2696,11 +2640,6 @@ int __init omap3xxx_hwmod_init(void)
goto put_node;
}
- if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
- r = omap_hwmod_register_links(h_aes);
- if (r < 0)
- goto put_node;
- }
of_node_put(bus);
/*
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-21 03:21:09 +0100