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path: root/drivers/gpu/drm/xe/xe_gsc.c
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Diffstat (limited to 'drivers/gpu/drm/xe/xe_gsc.c')
-rw-r--r--drivers/gpu/drm/xe/xe_gsc.c61
1 files changed, 56 insertions, 5 deletions
diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
index 8a137cb83318..6fbea70d3d36 100644
--- a/drivers/gpu/drm/xe/xe_gsc.c
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -8,6 +8,7 @@
#include <linux/delay.h>
#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
#include <generated/xe_wa_oob.h>
@@ -165,10 +166,11 @@ static int query_compatibility_version(struct xe_gsc *gsc)
return err;
}
- compat->major = version_query_rd(xe, &bo->vmap, rd_offset, compat_major);
- compat->minor = version_query_rd(xe, &bo->vmap, rd_offset, compat_minor);
+ compat->major = version_query_rd(xe, &bo->vmap, rd_offset, proj_major);
+ compat->minor = version_query_rd(xe, &bo->vmap, rd_offset, compat_major);
+ compat->patch = version_query_rd(xe, &bo->vmap, rd_offset, compat_minor);
- xe_gt_info(gt, "found GSC cv%u.%u\n", compat->major, compat->minor);
+ xe_gt_info(gt, "found GSC cv%u.%u.%u\n", compat->major, compat->minor, compat->patch);
out_bo:
xe_bo_unpin_map_no_vm(bo);
@@ -333,9 +335,11 @@ static int gsc_er_complete(struct xe_gt *gt)
if (er_status == GSCI_TIMER_STATUS_TIMER_EXPIRED) {
/*
* XXX: we should trigger an FLR here, but we don't have support
- * for that yet.
+ * for that yet. Since we can't recover from the error, we
+ * declare the device as wedged.
*/
xe_gt_err(gt, "GSC ER timed out!\n");
+ xe_device_declare_wedged(gt_to_xe(gt));
return -EIO;
}
@@ -513,13 +517,28 @@ out_bo:
void xe_gsc_load_start(struct xe_gsc *gsc)
{
struct xe_gt *gt = gsc_to_gt(gsc);
+ struct xe_device *xe = gt_to_xe(gt);
if (!xe_uc_fw_is_loadable(&gsc->fw) || !gsc->q)
return;
+ /*
+ * The GSC HW is only reset by driver FLR or D3cold entry. We don't
+ * support the former at runtime, while the latter is only supported on
+ * DGFX, for which we don't support GSC. Therefore, if GSC failed to
+ * load previously there is no need to try again because the HW is
+ * stuck in the error state.
+ */
+ xe_assert(xe, !IS_DGFX(xe));
+ if (xe_uc_fw_is_in_error_state(&gsc->fw))
+ return;
+
/* GSC FW survives GT reset and D3Hot */
if (gsc_fw_is_loaded(gt)) {
- xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_TRANSFERRED);
+ if (xe_gsc_proxy_init_done(gsc))
+ xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_RUNNING);
+ else
+ xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_TRANSFERRED);
return;
}
@@ -571,3 +590,35 @@ void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)
msleep(200);
}
}
+
+/**
+ * xe_gsc_print_info - print info about GSC FW status
+ * @gsc: the GSC structure
+ * @p: the printer to be used to print the info
+ */
+void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p)
+{
+ struct xe_gt *gt = gsc_to_gt(gsc);
+ int err;
+
+ xe_uc_fw_print(&gsc->fw, p);
+
+ drm_printf(p, "\tfound security version %u\n", gsc->security_version);
+
+ if (!xe_uc_fw_is_enabled(&gsc->fw))
+ return;
+
+ err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC);
+ if (err)
+ return;
+
+ drm_printf(p, "\nHECI1 FWSTS: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(gt, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(gt, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(gt, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(gt, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(gt, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));
+
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);
+}