linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: ingenic: Add .set_rate_hook() for PLL clocks	Aidan MacDonald	2022-10-27	1	-0/+3
*	clk: ingenic: Make PLL clock enable_bit and stable_bit optional	Aidan MacDonald	2022-10-27	1	-1/+13
*	clk: ingenic: Make PLL clock "od" field optional	Aidan MacDonald	2022-10-27	1	-8/+17
*	clk: ingenic: Allow specifying common clock flags	Aidan MacDonald	2022-05-18	1	-1/+1
*	clk: ingenic: Fix bugs with divided dividers	Paul Cercueil	2021-11-02	1	-3/+3
*	clk: ingenic: Support overriding PLLs M/N/OD calc algorithm	Paul Cercueil	2021-06-28	1	-13/+27
*	clk: ingenic: Remove pll_info.no_bypass_bit	Paul Cercueil	2021-06-28	1	-2/+2
*	clk: ingenic: Read bypass register only when there is one	Paul Cercueil	2021-06-28	1	-8/+11
*	clk: Support bypassing dividers	Paul Cercueil	2021-06-28	1	-11/+22
*	clk: ingenic: Fix divider calculation with div tables	Paul Cercueil	2020-12-20	1	-4/+10
*	clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate	Paul Cercueil	2020-10-14	1	-0/+2
*	clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT	Paul Cercueil	2020-10-14	1	-7/+7
*	clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL	Paul Cercueil	2020-10-14	1	-2/+7
*	clk: ingenic: Use readl_poll_timeout instead of custom loop	Paul Cercueil	2020-10-14	1	-26/+29
*	clk: ingenic: Use to_clk_info() macro for all clocks	Paul Cercueil	2020-10-14	1	-39/+15
*	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	周琰杰 (Zhou Yanjie)	2020-05-29	1	-3/+13
*	clk: Ingenic: Remove unnecessary spinlock when reading registers.	周琰杰 (Zhou Yanjie)	2020-05-29	1	-11/+1
*	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	2019-07-17	1	-6/+35
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\| *	clk: ingenic: Add support for divider tables	Paul Cercueil	2019-06-07	1	-6/+35
* \|	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	Thomas Gleixner	2019-05-30	1	-10/+1
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*	clk: Remove io.h from clk-provider.h	Stephen Boyd	2019-05-15	1	-0/+1
*	clk: ingenic: Remove set but not used variable 'enable'	YueHaibing	2019-02-26	1	-2/+1
*	clk: ingenic: Fix round_rate misbehaving with non-integer dividers	Paul Cercueil	2019-02-22	1	-5/+5
*	clk: ingenic: Support specifying "wait for clock stable" delay	Paul Cercueil	2018-06-02	1	-0/+3
*	clk: ingenic: Add support for clocks whose gate bit is inverted	Paul Cercueil	2018-06-02	1	-2/+3
*	clk: ingenic: Add code to enable/disable PLLs	Paul Cercueil	2018-01-18	1	-15/+74
*	clk: ingenic: support PLLs with no bypass bit	Paul Cercueil	2018-01-18	1	-1/+2
*	clk: ingenic: Fix recalc_rate for clocks with fixed divider	Paul Cercueil	2018-01-18	1	-0/+2
*	Update MIPS email addresses	Paul Burton	2017-11-03	1	-1/+1
*	clk: ingenic: Allow divider value to be divided	Harvey Hunt	2016-05-12	1	-1/+10
*	clk: ingenic: Include clk.h	Stephen Boyd	2015-07-20	1	-0/+1
*	clk: ingenic: add driver for Ingenic SoC CGU clocks	Paul Burton	2015-06-21	1	-0/+711