| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment | Geert Uytterhoeven | 2018-09-25 | 1 | -2/+2 |
| * | clk: renesas: r8a77990: Add missing I2C7 clock | Geert Uytterhoeven | 2018-08-31 | 1 | -0/+1 |
| * | clk: renesas: r8a77990: Correct RCLK handling | Geert Uytterhoeven | 2018-08-27 | 1 | -2/+10 |
| * | clk: renesas: cpg-mssr: Add support for R-Car E3 | Yoshihiro Shimoda | 2018-05-09 | 1 | -0/+289 |
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