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path: root/drivers/gpu/drm/i915/display/intel_ddi.c (follow)
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* drm/i915/display: Allow fastset for change in HDR infoframeChaitanya Kumar Borah2024-11-041-0/+11
* drm/i915/dp: Add FEC Enable Retry mechanismChaitanya Kumar Borah2024-11-041-23/+58
* drm/i915/dp: Track source OUI validity explicitlyImre Deak2024-10-311-0/+1
* drm/i915/dsi: convert to struct intel_displayJani Nikula2024-10-301-1/+1
* drm/i915/ddi: use string choice helpersR Sundar2024-10-221-1/+1
* drm/i915/dp: clean up intel_dp_test.[ch] interfaceJani Nikula2024-09-231-5/+1
* drm/i915/dp: split out intel_dp_test.[ch] to a dedicated fileJani Nikula2024-09-231-0/+1
* drm/i915/display: Enhance iterators for modeset en/disableAnkit Nautiyal2024-09-191-7/+7
* drm/i915/dp: Fix AUX IO power enabling for eDP PSRImre Deak2024-09-131-1/+1
* drm/i915/ddi: stop using dp_to_i915()Jani Nikula2024-09-031-7/+7
* drm/i915/hti: convert to struct intel_displayJani Nikula2024-08-161-1/+1
* drm/i915/bios: convert to struct intel_displayJani Nikula2024-08-121-1/+2
* drm/i915: Replace double blank with single blank after commaAndi Shyti2024-08-081-1/+1
* drm/i915/ddi: For an active output call the DP encoder sync_state() only for DPImre Deak2024-07-311-1/+2
* drm/i915/mtl: Skip PLL state verification in TBT modeImre Deak2024-06-281-5/+3
* drm/i915/display: For MTL+ platforms skip mg dp programmingImre Deak2024-06-261-0/+3
* drm/i915/dp: Use check link state work in the hotplug handlerImre Deak2024-06-131-6/+5
* drm/i915/dp: Pass atomic state to link training functionImre Deak2024-06-131-3/+3
* drm/i915/dp: Recheck link state after modesetImre Deak2024-06-131-0/+19
* drm/i915: Factor out function to modeset commit a set of pipesImre Deak2024-06-131-30/+1
* drm/i915: Rename bigjoiner master/slave to bigjoiner primary/secondaryStanislav Lisovskiy2024-06-121-3/+2
* drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy2024-06-121-2/+2
* drm/i915: pass dev_priv explicitly to TRANS_MSA_MISCJani Nikula2024-06-071-1/+2
* drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUSJani Nikula2024-06-071-1/+2
* drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTLJani Nikula2024-06-071-1/+2
* drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2Jani Nikula2024-06-071-3/+6
* drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTLJani Nikula2024-06-071-11/+18
* drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUGVille Syrjälä2024-06-061-3/+3
* drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuffVille Syrjälä2024-04-191-5/+5
* drm/i915/quirks: convert struct drm_i915_private to struct intel_displayJani Nikula2024-04-181-3/+3
* drm/i915: limit eDP MSO pipe only for display version 20 and belowLuca Coelho2024-04-181-2/+7
* drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä2024-04-171-4/+4
* drm/i915: Handle joined pipes inside hsw_crtc_enable()Stanislav Lisovskiy2024-04-111-4/+10
* drm/i915: Utilize intel_crtc_joined_pipe_mask() moreVille Syrjälä2024-04-111-16/+17
* drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst()Ville Syrjälä2024-04-111-14/+22
* drm/i915: Introduce intel_crtc_joined_pipe_mask()Ville Syrjälä2024-04-091-6/+5
* drm/i915: Disable port sync when bigjoiner is usedVille Syrjälä2024-04-081-0/+5
* drm/i915/psr: Unify panel replay enable/disable sinkJouni Högander2024-04-081-6/+5
* drm/i915/display: Read/Write Adaptive Sync SDPMitul Golani2024-04-041-0/+1
* drm/i915/display: use intel_encoder_is/to_* functionsJani Nikula2024-03-211-69/+47
* drm/i915/ddi: pass encoder to intel_wait_ddi_buf_active()Jani Nikula2024-03-211-5/+6
* drm/i915/dp: Increase idle pattern wait timeout to 2msShekhar Chauhan2024-03-141-1/+1
* drm/i915/dp: Call intel_dp_sync_state() always for DDI DP encodersImre Deak2024-02-271-1/+1
* drm/i915/dp: Allocate/free DP tunnel BW during modesetImre Deak2024-02-271-0/+1
* drm/i915/xe2lpd: Move registers to PICALucas De Marchi2024-01-301-9/+11
* drm/i915/xe2lpd: Move D2D enable/disableLucas De Marchi2024-01-301-10/+34
* drm/i915: Add intel_digital_port lock/unlock hooksImre Deak2024-01-081-0/+3
* drm/i915/display: Read PSR configuration before VSC SDPJouni Högander2023-12-221-2/+2
* drm/i915: Simplify intel_ddi_compute_min_voltage_level()Ville Syrjälä2023-12-131-4/+5
* drm/i915/mtl: Calculate the correct voltage level from port_clockVille Syrjälä2023-12-131-1/+3
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