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path: root/drivers/gpu/drm/i915/display/intel_dpll.c (follow)
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* drm/i915/display: convert I915_STATE_WARN() to struct intel_displayJani Nikula2024-10-291-4/+5
* drm/i915/panel: Convert panel code to intel_displayVille Syrjälä2024-10-231-9/+18
* drm/i915: remove IS_LP()Jani Nikula2024-10-021-2/+5
* drm/i915/display: fix typo in the commentYan Zhen2024-09-161-1/+1
* drm/i915/display: pass display to intel_crtc_for_pipe()Jani Nikula2024-09-051-1/+2
* drm/i915/pps: convert intel_pps.[ch] to struct intel_displayJani Nikula2024-09-031-3/+6
* drm/i915: pass dev_priv explicitly to DPLL_MDJani Nikula2024-06-071-7/+11
* drm/i915: pass dev_priv explicitly to DPLLJani Nikula2024-06-071-22/+23
* drm/i915/dpio: Extract vlv_dpio_phy_regs.hVille Syrjälä2024-04-301-0/+1
* drm/i915/dpio: Clean up the vlv/chv PHY register bitsVille Syrjälä2024-04-301-43/+42
* drm/i915/dpio: s/pipe/ch/Ville Syrjälä2024-04-301-24/+25
* drm/i915/dpio: s/port/ch/Ville Syrjälä2024-04-301-27/+27
* drm/i915/dpio: Rename some variablesVille Syrjälä2024-04-301-49/+48
* drm/i915/dpio: Remove pointless variables from vlv/chv DPLL codeVille Syrjälä2024-04-301-36/+28
* drm/i915/dpio: Fix VLV DPIO PLL register dword numberingVille Syrjälä2024-04-301-9/+9
* drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/Ville Syrjälä2024-04-301-1/+1
* drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/Ville Syrjälä2024-04-301-4/+4
* drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä2024-04-171-1/+1
* drm/i915: Carve up struct intel_dpll_hw_stateVille Syrjälä2024-04-171-15/+16
* drm/i915: Add local DPLL 'hw_state' variablesVille Syrjälä2024-04-171-46/+56
* drm/i915: s/pipe_config/crtc_state/ in legacy PLL codeVille Syrjälä2024-04-171-15/+15
* drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()Ville Syrjälä2024-04-171-12/+9
* drm/i915: Modernize i9xx_pll_refclk()Ville Syrjälä2024-04-171-8/+7
* drm/i915: Inline {i9xx,ilk}_update_pll_dividers()Ville Syrjälä2024-04-171-33/+13
* drm/i915: Extract {i9xx,i8xx,ilk,vlv,chv}_dpll()Ville Syrjälä2024-04-171-33/+68
* drm/i915: Extract i965_dpll_md()Ville Syrjälä2024-04-171-9/+9
* drm/i915: Extract i9xx_dpll_get_hw_state()Ville Syrjälä2024-04-171-0/+30
* drm/i915: Extract ilk_dpll_compute_fp()Ville Syrjälä2024-04-171-10/+12
* drm/i915: Extract ilk_fb_cb_factor()Ville Syrjälä2024-04-171-15/+17
* drm/i915: convert vlv_dpio_read()/write() from pipe to phyJani Nikula2023-11-171-51/+55
* drm/i915: move *_crtc_clock_get() to intel_dpll.cJani Nikula2023-11-171-2/+173
* drm/i915/display: Abstract C10/C20 pll calculationLucas De Marchi2023-10-301-6/+1
* drm/i915/display: Use correct method to free crtc_stateSuraj Kandpal2023-10-111-1/+2
* drm/i915: Fully populate crtc_state->dpllVille Syrjälä2023-08-241-2/+15
* drm/i915: Don't warn about zero N/P in *_calc_dpll_params()Ville Syrjälä2023-08-241-17/+20
* drm/i915/dpll: drop unused but set variables bestn and bestm1Jani Nikula2023-06-071-3/+1
* drm/i915/display: add i915 parameter to I915_STATE_WARN()Jani Nikula2023-05-151-1/+1
* drm/i915/mtl: C20 port clock calculationMika Kahola2023-04-281-0/+2
* drm/i915/mtl: Add Support for C10 PHY message bus and pll programmingRadhakrishna Sripada2023-04-141-1/+32
* drm/i915: move chv_dpll_md and bxt_phy_grc to display sub-struct under stateJani Nikula2023-01-181-1/+1
* drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula2022-11-111-0/+1
* drm/i915/dpio: un-inline the vlv phy/channel mapping functionsJani Nikula2022-11-031-0/+1
* drm/i915: Fix TV encoder clock computationVille Syrjälä2022-09-131-2/+6
* drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä2022-09-081-3/+57
* drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()Ville Syrjälä2022-09-081-4/+2
* drm/i915: Do .crtc_compute_clock() earlierVille Syrjälä2022-09-081-3/+0
* drm/i915: move vbt to display.vbtJani Nikula2022-08-311-7/+7
* drm/i915: move dpll_funcs to display.funcsJani Nikula2022-08-291-12/+12
* drm/i915: Clean up DPLL related debugsVille Syrjälä2022-05-311-49/+26
* drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä2022-05-311-2/+12
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