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path: root/drivers/gpu/drm/i915/display/intel_psr_regs.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* drm/i915/xe3lpd: Add new bit range of MAX swing setupSuraj Kandpal2024-10-231-1/+1
* drm/i915:Remove unused parameter in marcoHe Lugang2024-10-021-2/+2
* drm/i915/reg: fix transcoder timing register styleJani Nikula2024-09-111-0/+1
* intel_alpm: Fix wrong offset for PORT_ALPM_* registersJouni Högander2024-06-191-2/+4
* drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()Ville Syrjälä2024-05-231-45/+0
* drm/i915: Rename selective fetch plane registersVille Syrjälä2024-05-221-5/+5
* drm/i915: Simplify PIPESRC_ERLY_TPT definitionVille Syrjälä2024-05-221-2/+2
* drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wideJouni Högander2024-05-201-0/+4
* drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTLJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to PORT_ALPM_CTLJani Nikula2024-05-061-1/+1
* FIXME drm/i915: pass dev_priv explicitly to ALPM_CTL2Jani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to ALPM_CTLJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPTJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTLJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to PSR2_SU_STATUSJani Nikula2024-05-061-2/+2
* drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUSJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to PSR_EVENTJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to EDP_PSR2_CTLJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUGJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNTJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to EDP_PSR_STATUSJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATAJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTLJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to TRANS_PSR_IIRJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to TRANS_PSR_IMRJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to EDP_PSR_CTLJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv explicitly to TRANS_EXITLINEJani Nikula2024-05-061-1/+1
* drm/i915: pass dev_priv to _MMIO_PIPE2, _MMIO_TRANS2, _MMIO_CURSOR2Jani Nikula2024-04-251-19/+19
* drm/i915/psr: Add missing ALPM AUX-Less register definitionsJouni Högander2024-04-021-4/+8
* drm/i915/alpm: Add ALPM register definitionsJouni Högander2024-02-071-0/+57
* drm/i915/psr: Enable psr2 early transport as possibleJouni Högander2024-01-091-0/+1
* drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transportJouni Högander2024-01-091-0/+5
* drm/i915/display: Support PSR entry VSC packet to be transmitted one frame ea...Mika Kahola2023-11-071-0/+2
* drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setupVille Syrjälä2023-06-161-0/+12
* drm/i915/psr: Reintroduce HSW PSR1 registersVille Syrjälä2023-06-161-0/+4
* drm/i915/psr: Fix BDW PSR AUX CH data register offsetsVille Syrjälä2023-06-161-1/+1
* drm/i915/psr: Define more PSR mask bitsVille Syrjälä2023-04-201-2/+12
* drm/i915/psr: Clean up PSR register defininitionsVille Syrjälä2023-04-201-96/+101
* drm/i915/psr: split out PSR regs to a separate fileJani Nikula2023-04-041-0/+260
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