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path: root/drivers/gpu/drm/i915/display/intel_vblank.c (follow)
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* drm/i915/dsb: Use intel_color_uses_dsb()Ville Syrjälä2024-06-051-1/+3
* drm/i915: Move intel_crtc_scanline_offset()Ville Syrjälä2024-05-311-38/+38
* drm/i915: Simplify scanline_offset handling for gen2Ville Syrjälä2024-05-311-5/+3
* drm/i915: Extract intel_mode_vtotal()Ville Syrjälä2024-05-311-23/+17
* drm/i915: Extract intel_mode_vblank_end()Ville Syrjälä2024-05-311-4/+12
* drm/i915: Reuse intel_mode_vblank_start()Ville Syrjälä2024-05-311-6/+3
* drm/i915: Use drm_crtc_vblank_crtc()Ville Syrjälä2024-05-081-11/+5
* drm/i915: Move intel_vblank_evade() & co. into intel_vblank.cVille Syrjälä2024-01-221-0/+130
* drm/i915: handle uncore spinlock when not availableLuca Coelho2023-12-071-10/+41
* drm/i915: Introduce intel_crtc_scanline_to_hw()Ville Syrjälä2023-09-271-0/+14
* drm/i915: Use min() instead of hand rolling itVille Syrjälä2023-04-131-2/+1
* drm/i915/vrr: Tell intel_crtc_update_active_timings() about VRR explicitlyVille Syrjälä2023-04-121-3/+9
* drm/i915: Extract intel_crtc_scanline_offset()Ville Syrjälä2023-03-181-41/+48
* drm/i915: Relocate intel_crtc_update_active_timings()Ville Syrjälä2023-03-181-0/+85
* drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä2023-02-171-2/+2
* drm/i915/vblank: add and use intel_de_read64_2x32() to read vblank counterJani Nikula2023-01-181-19/+6
* drm/i915/vblank: use intel_de_read()Jani Nikula2023-01-181-1/+1
* drm/i915/display: move more scanline functions to intel_vblank.[ch]Jani Nikula2023-01-181-0/+35
* drm/i915/irq: split out vblank/scanline code to intel_vblank.[ch]Jani Nikula2023-01-181-0/+419