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path: root/drivers/gpu/drm/i915/display/skl_watermark.h (follow)
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* drm/i915: Handle SKL+ WM/DDB registers next to all other plane registersVille Syrjälä2024-05-151-5/+8
* drm/i915/display: Disable SAGV on bw init, to force QGV point recalculationStanislav Lisovskiy2024-04-191-0/+1
* drm/i915: Use a plain old int for the cdclk/mdclk ratioVille Syrjälä2024-04-041-2/+4
* drm/i915: Implement vblank synchronized MBUS join changesStanislav Lisovskiy2024-04-041-1/+2
* drm/i915: Use container_of_const() for statesVille Syrjälä2024-03-151-1/+3
* drm/i915/xe2lpd: Support MDCLK:CDCLK ratio changesGustavo Sousa2024-03-131-0/+1
* drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_stateGustavo Sousa2024-03-131-0/+3
* drm/i915/lnl: Program PKGC_LATENCY registerSuraj Kandpal2024-02-231-2/+2
* drm/i915: Simplify watermark state checker calling conventionVille Syrjälä2023-10-061-2/+2
* drm/i915: Constify watermark state checkerVille Syrjälä2023-10-061-1/+1
* drm/i915: Introduce skl_watermark_max_latency()Ville Syrjälä2023-09-271-0/+2
* drm/i915: rename intel_pm_types.h -> display/intel_wm_types.hJani Nikula2023-02-161-1/+1
* drm/i915/wm: add .get_hw_state to watermark funcsJani Nikula2023-02-151-3/+0
* drm/i915: Expose SAGV state via debugfsVille Syrjälä2023-02-011-1/+1
* drm/i915/display: add intel_display_limits.h for key enumsJani Nikula2023-01-251-1/+1
* drm/i915/ipc: move IPC debugfs to skl_watermark.cJani Nikula2022-09-131-0/+1
* drm/i915/ipc: refactor and rename IPC functionsJani Nikula2022-09-131-2/+3
* drm/i915: Extract skl_watermark.cVille Syrjälä2022-09-091-0/+78
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