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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
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* drm/i915/icl: restore WaEnableFloatBlendOptimizationTalha Nassar2019-02-011-0/+3
* drm/i915: Force background color to black for gen9+ (v2)Matt Roper2019-01-311-0/+6
* drm/i915/icl: use tc_port in MG_PLL macrosLucas De Marchi2019-01-291-26/+26
* drm/i915/tv: Generate better pipe timings for TV encoderVille Syrjälä2019-01-251-0/+1
* drm/i915: Add PSR2 selective update status registers and bits definitionsJosé Roberto de Souza2019-01-231-0/+9
* drm/i915/dp: remove PANEL_POWER_OFF macro and its useJani Nikula2019-01-181-1/+0
* drm/i915: small isolated c99 types to kernel types switchJani Nikula2019-01-171-2/+2
* drm/i915/cnl: Fix CNL macros for Voltage Swing programmingAditya Swarup2019-01-151-7/+7
* drm/i915: always use INTEL_INFO() to access device infoJani Nikula2019-01-021-6/+6
* drm/i915/reg: abstract display_mmio_offset accessJani Nikula2019-01-021-93/+95
* drm/i915/icl: combo port vswing programming changes per BSPECClint Taylor2018-12-181-0/+4
* drm/i915/icl: Mind the SFC units when resetting VD or VEBox enginesOscar Mateo2018-12-131-0/+18
* drm/i915/icl: Define Panel power ctrl registerMadhav Chauhan2018-12-031-0/+11
* drm/i915/icl: Define missing bitfield for shortplug regMadhav Chauhan2018-12-031-0/+1
* i915/dp/fec: Configure the Forward Error Correction bits.Anusha Srivatsa2018-11-291-0/+2
* drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPsManasi Navare2018-11-291-0/+1
* drm/i915: Make CHICKEN_TRANS reg not depend on enum valueImre Deak2018-11-211-3/+4
* drm/i915: Make EDP PSR flags not depend on enum valuesImre Deak2018-11-211-3/+7
* Revert "drm/i915/perf: add a parameter to control the size of OA buffer"Joonas Lahtinen2018-11-191-2/+0
* drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IAMika Kuoppala2018-11-141-3/+1
* drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DENPaulo Zanoni2018-11-141-2/+1
* drm/i915: Polish the skl+ plane keyval/msk/max register setupVille Syrjälä2018-11-091-1/+1
* drm/i915/icl: Define Plane Input CSC Coefficient RegistersUma Shankar2018-11-061-0/+50
* drm/i915/fia: FIA registers offset implementation.Anusha Srivatsa2018-11-021-4/+6
* drm/i915: also group device info array helper macros with othersJani Nikula2018-11-021-12/+14
* drm/i915: reorder and reindent the register choosing helper wrappersJani Nikula2018-11-021-14/+17
* drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()Jani Nikula2018-11-021-1/+1
* drm/i915: remove palette_offsets from device info in favor of _PICK()Jani Nikula2018-11-021-9/+7
* drm/i915/icl: Fix DSS_CTL register namesAnusha Srivatsa2018-11-021-11/+11
* drm/i915/icl: WaAllowUMDToModifySamplerModeOscar Mateo2018-11-011-0/+2
* drm/i915/icl: Add WaEnable32PlaneModeRadhakrishna Sripada2018-11-011-0/+1
* drm/i915/icl: Add DSS_CTL RegistersAnusha Srivatsa2018-11-011-0/+33
* drm/i915/icl: Add DSI packet payload/header registersMadhav Chauhan2018-11-011-0/+22
* drm/i915/icl: Fix the macros for DFLEXDPMLE register bitsManasi Navare2018-11-011-2/+6
* drm/i915/dsc: Add slice_row_per_frame in DSC PPS programmingAnusha Srivatsa2018-10-311-0/+1
* drm/i915/icl: Define DSI timeout registersMadhav Chauhan2018-10-311-0/+43
* drm/i915: Move VIDEO_DIP_CTL definitions to their right place.Dhinakaran Pandiyan2018-10-291-10/+9
* drm/i915: Fix VIDEO_DIP_CTL bit shiftsDhinakaran Pandiyan2018-10-291-6/+6
* drm/i915: Define Intel HDCP2.2 registersRamalingam C2018-10-291-0/+32
* drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.Maarten Lankhorst2018-10-241-0/+1
* drm/i915/gen11: Program the chroma upsampler for HDR planes.Maarten Lankhorst2018-10-241-0/+22
* drm/i915/gen11: Program the scalers correctly for planar formats, v3.Maarten Lankhorst2018-10-241-1/+3
* drm/i915/perf: add a parameter to control the size of OA bufferLionel Landwerlin2018-10-231-0/+2
* drm/i915/icl: Define DSI panel programming registersMadhav Chauhan2018-10-221-0/+38
* drm/i915/icl: Define TRANS_CONF register for DSIMadhav Chauhan2018-10-221-0/+8
* drm/i915/icl: Define DSI transcoder timing registersMadhav Chauhan2018-10-221-0/+14
* drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registersMadhav Chauhan2018-10-221-0/+17
* drm/i915/icl: Define TRANS_DSI_FUNC_CONF registerMadhav Chauhan2018-10-221-0/+45
* drm/i915/icl: Add macros for MMIO of DSI transcoder registersMadhav Chauhan2018-10-221-0/+4
* drm/i915/icl: Fix DDI/TC port clk_off bitsMahesh Kumar2018-10-161-0/+3
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