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path: root/drivers/phy/cadence/phy-cadence-sierra.c (follow)
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* Merge tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy...Linus Torvalds2024-11-271-1/+1
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| * phy: Switch back to struct platform_driver::remove()Uwe Kleine-König2024-10-171-1/+1
* | phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control registerBartosz Wawrzyniak2024-10-071-10/+11
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* phy: cadence: sierra: Simplify with scoped for each OF child loopKrzysztof Kozlowski2024-08-301-5/+2
* phy: cadence: Sierra: Constify a u32[]Christophe JAILLET2024-07-311-1/+1
* phy: cadence: Sierra: Constify struct cdns_sierra_valsChristophe JAILLET2024-07-311-40/+40
* phy: cadence: Sierra: Constify struct cdns_reg_pairsChristophe JAILLET2024-07-311-3/+3
* phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki2023-07-121-0/+98
* phy: cadence: sierra: Add a determine_rate hookMaxime Ripard2023-06-091-0/+1
* phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configurationSwapnil Jakhade2023-04-121-2/+139
* phy: cadence: Sierra: Use clk_parent_data to provide parent informationLars-Peter Clausen2023-03-311-42/+15
* phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`Lars-Peter Clausen2023-03-311-20/+26
* phy: cadence: phy-cadence-sierra: Convert to platform remove callback returni...Uwe Kleine-König2023-03-201-4/+2
* phy: cadence: Sierra: Remove unused `regmap` field from state structLars-Peter Clausen2022-07-081-1/+0
* phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configurationSwapnil Jakhade2022-04-131-3/+190
* phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju2022-02-071-25/+57
* phy: cadence: Sierra: fix error handling bugs in probe()Dan Carpenter2022-01-241-14/+21
* phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade2021-12-271-1/+108
* phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade2021-12-271-1/+376
* phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade2021-12-271-8/+190
* phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade2021-12-271-5/+26
* phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade2021-12-271-1/+213
* phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade2021-12-271-1/+72
* phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade2021-12-271-0/+45
* phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade2021-12-271-0/+38
* phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ...Swapnil Jakhade2021-12-271-10/+11
* phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade2021-12-271-1/+5
* phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade2021-12-271-56/+139
* phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade2021-12-271-9/+4
* phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()Wang Wensheng2021-05-311-0/+1
* phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I2021-03-311-3/+37
* phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I2021-03-311-3/+264
* phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I2021-03-311-0/+3
* phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I2021-03-311-10/+15
* phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I2021-03-311-2/+2
* phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I2021-03-311-11/+25
* phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I2021-03-311-22/+35
* phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I2021-03-311-0/+4
* phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I2021-03-311-1/+6
* phy: cadence: convert to devm_platform_ioremap_resourceChunfeng Yun2020-11-161-3/+1
* phy: cadence: Sierra: Constify static structsRikard Falkeborn2020-09-161-12/+12
* phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar2020-05-181-13/+14
* phy: cadence: Sierra: add phy_reset hookRoger Quadros2020-01-141-0/+10
* phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King2020-01-141-1/+1
* phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I2020-01-081-1/+1
* phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to...Kishon Vijay Abraham I2020-01-081-0/+21
* phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I2020-01-081-1/+21
* phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I2020-01-081-1/+32
* phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I2020-01-081-1/+1
* phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ex...Anil Varughese2020-01-081-96/+254
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-23 21:44:45 +0100