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| author | Elizarova, Alina <alina.elizarova@intel.com> | 2024-12-04 19:29:23 +0100 |
|---|---|---|
| committer | Tomas Mraz <tomas@openssl.org> | 2024-12-13 14:51:22 +0100 |
| commit | acc26552369bb39de6d30737fc30a6bc4f2ebbae (patch) | |
| tree | e8cb792d50fdc994c1746eaa5ffa40ab21d875d9 /crypto/x86cpuid.pl | |
| parent | Fix typo in SSL_get_shared_sigalgs docs (diff) | |
| download | openssl-acc26552369bb39de6d30737fc30a6bc4f2ebbae.tar.xz openssl-acc26552369bb39de6d30737fc30a6bc4f2ebbae.zip | |
Extension of OPENSSL_ia32cap to accommodate additional CPUID bits
bits 128 - 191 CPUID.(EAX=07H,ECX=0H).EDX and CPUID.(EAX=07H,ECX=1H).EAX
bits 192 - 255 CPUID.(EAX=07H,ECX=1H).EDX and CPUID.(EAX=07H,ECX=1H).EBX
bits 256 - 319 CPUID.(EAX=07H,ECX=1H).ECX and CPUID.(EAX=24H,ECX=0H).EBX
Reviewed-by: Matt Caswell <matt@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/25709)
Diffstat (limited to 'crypto/x86cpuid.pl')
| -rw-r--r-- | crypto/x86cpuid.pl | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/crypto/x86cpuid.pl b/crypto/x86cpuid.pl index a7bcb27e26..35e2c5b0a5 100644 --- a/crypto/x86cpuid.pl +++ b/crypto/x86cpuid.pl @@ -137,7 +137,28 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } &mov ("eax",7); &xor ("ecx","ecx"); &cpuid (); - &mov (&DWP(8,"edi"),"ebx"); # save extended feature flag + &mov (&DWP(8,"edi"),"ebx"); # save cpuid(EAX=0x7, ECX=0x0).EBX to OPENSSL_ia32cap_P[2] + &mov (&DWP(12,"edi"),"ecx"); # save cpuid(EAX=0x7, ECX=0x0).ECX to OPENSSL_ia32cap_P[3] + &mov (&DWP(16,"edi"),"edx"); # save cpuid(EAX=0x7, ECX=0x0).EDX to OPENSSL_ia32cap_P[4] + &cmp ("eax",1); # Do we have cpuid(EAX=0x7, ECX=0x1)? + &jb (&label("no_extended_info")); + &mov ("eax",7); + &mov ("ecx",1); + &cpuid (); # cpuid(EAX=0x7, ECX=0x1) + &mov (&DWP(20,"edi"),"eax"); # save cpuid(EAX=0x7, ECX=0x1).EAX to OPENSSL_ia32cap_P[5] + &mov (&DWP(24,"edi"),"edx"); # save cpuid(EAX=0x7, ECX=0x1).EDX to OPENSSL_ia32cap_P[6] + &mov (&DWP(28,"edi"),"ebx"); # save cpuid(EAX=0x7, ECX=0x1).EBX to OPENSSL_ia32cap_P[7] + &mov (&DWP(32,"edi"),"ecx"); # save cpuid(EAX=0x7, ECX=0x1).ECX to OPENSSL_ia32cap_P[8] + + &and ("edx",0x80000); # Mask cpuid(EAX=0x7, ECX=0x1).EDX bit 19 to detect AVX10 support + &cmp ("edx",0x0); + &je (&label("no_extended_info")); + + &mov ("eax",0x24); # Have AVX10 Support, query for details + &mov ("ecx",0x0); + &cpuid (); # cpuid(EAX=0x24, ECX=0x0) AVX10 Leaf + &mov (&DWP(36,"edi"),"ebx"); # save cpuid(EAX=0x24, ECX=0x0).EBX to OPENSSL_ia32cap_P[9] + &set_label("no_extended_info"); &bt ("ebp",27); # check OSXSAVE bit @@ -154,6 +175,9 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } &and ("esi",0xfeffffff); # clear FXSR &set_label("clear_avx"); &and ("ebp",0xefffe7ff); # clear AVX, FMA and AMD XOP bits + &and (&DWP(20,"edi"),0xff7fffff); # ~(1<<23) clear AVXIFMA, + # which is VEX-encoded + # and requires YMM state support &and (&DWP(8,"edi"),0xffffffdf); # clear AVX2 &set_label("done"); &mov ("eax","esi"); |