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* cxl/region: Fix region creation for greater than x2 switchesHuaisheng Ye2024-12-101-7/+18
* cxl/pci: Check dport->regs.rcd_pcie_cap availability before accessingLi Ming2024-12-101-0/+3
* cxl/pci: Fix potential bogus return value upon successful probingDavidlohr Bueso2024-12-101-2/+1
* module: Convert symbol namespace to string literalPeter Zijlstra2024-12-0216-109/+109
* Merge tag 'driver-core-6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2024-11-291-1/+1
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| * sysfs: treewide: constify attribute callback of bin_is_visible()Thomas Weißschuh2024-11-051-1/+1
* | Merge tag 'cxl-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds2024-11-227-47/+193
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| * Merge branch 'cxl/for-6.13/dcd-prep' into cxl-for-nextDave Jiang2024-11-083-36/+21
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| | * cxl/region: Refactor common create region codeIra Weiny2024-11-081-17/+11
| | * cxl/hdm: Use guard() in cxl_dpa_set_mode()Ira Weiny2024-11-081-15/+6
| | * cxl/pci: Delay event buffer allocationIra Weiny2024-11-081-4/+4
| * | Merge branch 'cxl/for-6.12/printf' into cxl-for-nextDave Jiang2024-10-281-4/+4
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| | * | cxl/cdat: Use %pra for dpa range outputsIra Weiny2024-10-281-4/+4
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| * | cxl: downgrade a warning message to debug level in cxl_probe_component_regs()Coly Li2024-10-281-1/+1
| * | cxl/pci: Add sysfs attribute for CXL 1.1 device link statusKobayashi,Daisuke2024-10-281-0/+78
| * | cxl/core/regs: Add rcd_pcie_cap initializationKobayashi,Daisuke2024-10-284-6/+89
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* | cxl/port: Prevent out-of-order decoder allocationDan Williams2024-10-251-10/+33
* | cxl/port: Fix use-after-free, permit out-of-order decoder shutdownDan Williams2024-10-253-44/+57
* | cxl/acpi: Ensure ports ready at cxl_acpi_probe() returnDan Williams2024-10-251-0/+7
* | cxl/port: Fix cxl_bus_rescan() vs bus_rescan_devices()Dan Williams2024-10-251-3/+10
* | cxl/port: Fix CXL port initialization order when the subsystem is built-inDan Williams2024-10-253-7/+31
* | cxl/events: Fix Trace DRAM Event RecordShiju Jose2024-10-251-3/+14
* | cxl/core: Return error when cxl_endpoint_gather_bandwidth() handles a non-PCI...Li Zhijian2024-10-241-0/+3
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* move asm/unaligned.h to linux/unaligned.hAl Viro2024-10-025-5/+5
* Merge tag 'cxl-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds2024-09-2714-381/+926
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| * cxl: Calculate region bandwidth of targets with shared upstream linkDave Jiang2024-09-236-10/+537
| * cxl: Preserve the CDAT access_coordinate for an endpointDave Jiang2024-09-232-4/+8
| * cxl: Fix comment regarding cxl_query_cmd() return dataDave Jiang2024-09-191-1/+1
| * cxl: Convert cxl_internal_send_cmd() to use 'struct cxl_mailbox' as inputDave Jiang2024-09-126-44/+54
| * cxl: Move mailbox related bits to the same contextDave Jiang2024-09-125-62/+116
| * cxl: move cxl headers to new include/cxl/ directoryDave Jiang2024-09-102-2/+2
| * cxl/region: Remove lock from memory notifier callbackIra Weiny2024-09-091-24/+30
| * cxl/pci: simplify the check of mem_enabled in cxl_hdm_decode_init()Yanfei Xu2024-09-091-10/+11
| * cxl/pci: Check Mem_info_valid bit for each applicable DVSECYanfei Xu2024-09-091-4/+4
| * cxl/pci: Remove duplicated implementation of waiting for memory_info_validYanfei Xu2024-09-093-38/+7
| * cxl/pci: Fix to record only non-zero rangesYanfei Xu2024-09-091-7/+1
| * cxl/pci: Remove duplicate host_bridge->native_aer checkingLi Ming2024-09-041-11/+6
| * cxl/pci: cxl_dport_map_rch_aer() cleanupLi Ming2024-09-041-20/+13
| * cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()Li Ming2024-09-043-7/+13
| * cxl/port: Refactor __devm_cxl_add_port() to drop goto patternLi Ming2024-09-031-24/+35
| * cxl/port: Use scoped_guard()/guard() to drop device_lock() for cxl_portLi Ming2024-09-035-87/+72
| * cxl/port: Use __free() to drop put_device() for cxl_portLi Ming2024-09-035-29/+20
| * cxl: Remove duplicate included header file core.hHongbo Li2024-09-031-1/+0
| * cxl/port: Convert to use ERR_CAST()Yuesong Li2024-09-031-1/+1
* | mm: make range-to-target_node lookup facility a part of numa_memblksMike Rapoport (Microsoft)2024-09-041-1/+1
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* cxl/pci: Get AER capability address from RCRB only for RCH dportLi Ming2024-08-101-4/+6
* Merge tag 'cxl-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds2024-07-2813-146/+174
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| * cxl/core/pci: Move reading of control register to immediately before usageForyun Ma2024-07-171-4/+4
| * Merge branch 'for-6.11/xor_fixes' into cxl-for-nextDave Jiang2024-07-127-112/+76
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| | * cxl: Remove defunct code calculating host bridge target positionsAlison Schofield2024-07-123-84/+4
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