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path: root/drivers/gpu/drm (follow)
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* drm/i915: Fix plane allocation/free functionsMaarten Lankhorst2018-11-153-51/+23
* drm/i915: Remove special case for power well 1/MISC_IO state verificationImre Deak2018-11-141-8/+7
* drm/i915: Use proper bool bitfield initializer in power well descsImre Deak2018-11-141-11/+11
* drm/i915/gen9_bc: Work around DMC bug zeroing power well requestsImre Deak2018-11-141-1/+15
* drm/i915: Fix icl workarounds whitespacesMika Kuoppala2018-11-141-11/+16
* drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IAMika Kuoppala2018-11-142-5/+4
* drm/i915/icl: Drop spurious register read from icl_dbuf_slices_updateMika Kuoppala2018-11-141-3/+1
* drm/i915: add ICP support to cnp_rawclk() and kill icp_rawclk()Paulo Zanoni2018-11-141-29/+8
* drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DENPaulo Zanoni2018-11-142-5/+4
* drm/i915/cnp+: update to the new RAWCLK_FREQ recommendationsPaulo Zanoni2018-11-141-3/+3
* drm/i915: Determine DSI panel orientation from VBTVille Syrjälä2018-11-135-1/+53
* drm/i915: Fix the VLV/CHV DSI panel orientation hw readoutVille Syrjälä2018-11-131-13/+43
* drm/i915: Move skip_intermediate_wm handling into ilk_compute_intermediate_wm()Ville Syrjälä2018-11-132-7/+3
* drm/i915: Account for scale factor when calculating initial phaseVille Syrjälä2018-11-133-10/+57
* drm/i915: Always write both TILEOFF and LINOFF plane registersVille Syrjälä2018-11-131-14/+7
* drm/i915: Switch LSPCON to PCON mode if it's in LS modeVille Syrjälä2018-11-131-1/+1
* drm/i915: fix broadwell EU computationLionel Landwerlin2018-11-121-1/+1
* drm/i915: Clean up the baseline bpp computationVille Syrjälä2018-11-121-18/+24
* drm/i915: Remove pointless goto failVille Syrjälä2018-11-121-12/+9
* drm/i915: Handle -EDEADLK from ironlake_check_fdi_lanes()Ville Syrjälä2018-11-121-0/+7
* drm/i915/query: fix subslice lengthDaniele Ceraolo Spurio2018-11-091-2/+1
* drm/i915: fix subslice mask array sizeDaniele Ceraolo Spurio2018-11-091-1/+1
* drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked()José Roberto de Souza2018-11-091-16/+9
* drm/i915/icl: Reset PSR interruptionsJosé Roberto de Souza2018-11-091-0/+3
* drm/i915/psr: Always wait for idle state when disabling PSRJosé Roberto de Souza2018-11-091-23/+18
* drm/i915/psr: Use intel_psr_exit() in intel_psr_disable_source()José Roberto de Souza2018-11-091-29/+21
* drm/i915: Generalize skl_ddb_allocation_overlaps()Ville Syrjälä2018-11-093-19/+15
* drm/i915: Clean up skl+ PLANE_POS vs. scaler handlingVille Syrjälä2018-11-091-7/+9
* drm/i915: Polish the skl+ plane keyval/msk/max register setupVille Syrjälä2018-11-092-14/+10
* drm/i915: Remove the PS_PWR_GATE write from skl_program_scaler()Ville Syrjälä2018-11-091-1/+0
* drm/i915/mst: Drop pre_pll_enable null checkJosé Roberto de Souza2018-11-091-2/+1
* drm/i915: Release DDI power well references in MST portsJosé Roberto de Souza2018-11-091-0/+15
* drm/i915: Reuse the aux_domain cachedJosé Roberto de Souza2018-11-091-2/+1
* drm/i915: Sanitize PCH port transcoder select on IBXVille Syrjälä2018-11-091-0/+63
* drm/i915: Fix hpd handling for pins with two encodersVille Syrjälä2018-11-091-13/+42
* drm/i915/icl: Fix PLL mapping sanitization for DP portsImre Deak2018-11-091-2/+25
* drm/i915/ddi: Add more sanity check to the encoder HW readoutImre Deak2018-11-091-24/+52
* drm/i915: Track rcu_head for our idle workerChris Wilson2018-11-091-0/+3
* drm/i915: Initialise the obj->rcu headChris Wilson2018-11-091-0/+9
* drm/i915: Keep overlay functions naming consistentJosé Roberto de Souza2018-11-094-6/+6
* drm/i915: Move intel_init_ipc() call to i915_load_modeset_init()José Roberto de Souza2018-11-091-2/+2
* drm/i915: Move FBC init and cleanup calls to modeset functionsJosé Roberto de Souza2018-11-093-3/+4
* drm/i915: Move drm_vblank_init() to i915_load_modeset_init()José Roberto de Souza2018-11-091-12/+7
* drm/i915: remove padding from struct skl_wm_levelPaulo Zanoni2018-11-091-1/+1
* drm/i915: Set MI_INVALIDATE_BSD for all video-decode enginesChris Wilson2018-11-081-1/+1
* drm/i915/icl: Fix port B combo PHY context loss after DC transitionsImre Deak2018-11-081-0/+8
* drm/i915/icl: Skip init for an already enabled combo PHYImre Deak2018-11-081-0/+6
* drm/i915/cnl+: Verify combo PHY HW state during PHY uninitImre Deak2018-11-081-2/+101
* drm/i915/cnl+: Move the combo PHY init/uninit code to a new fileImre Deak2018-11-084-119/+156
* drm/i915/icl: Fix combo PHY uninitImre Deak2018-11-081-0/+4
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