diff options
| author | Peng Fan <peng.fan@nxp.com> | 2022-08-30 05:31:33 +0200 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2022-09-19 12:06:45 +0200 |
| commit | 2b66f02e2de174c2a9bdf60160a1d9963dc7ca2c (patch) | |
| tree | 6d956a947b65635fb246cefc61b43af35cdfd30b /drivers/clk/imx/clk.h | |
| parent | clk: imx: clk-composite-93: check slice busy (diff) | |
| download | linux-2b66f02e2de174c2a9bdf60160a1d9963dc7ca2c.tar.xz linux-2b66f02e2de174c2a9bdf60160a1d9963dc7ca2c.zip | |
clk: imx: clk-composite-93: check white_list
The CCM ROOT AUTHEN register WHITE_LIST indicate:
Each bit in this field represent for one domain. Bit16~Bit31 represent
for DOMAIN0~DOMAIN15 respectively. Only corresponding bit of the domains
is set to 1 can change the registers of this Clock Root.
i.MX93 DID is 3, so if BIT(3 + WHITE_LIST_SHIFT) is 0, the clk should be
set to read only. To make the imx93_clk_composite_flags be reusable,
add a new parameter named did(domain id);
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220830033137.4149542-5-peng.fan@oss.nxp.com
Diffstat (limited to 'drivers/clk/imx/clk.h')
| -rw-r--r-- | drivers/clk/imx/clk.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 5061a06468df..396a5ea75083 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -445,9 +445,10 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 domain_id, unsigned long flags); -#define imx93_clk_composite(name, parent_names, num_parents, reg) \ - imx93_clk_composite_flags(name, parent_names, num_parents, reg, \ +#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ + imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, |